Hardware multi-stream multi-standard video decoder device

摘要

A hardware multi-stream multi-standard video decoder device. A command parser accesses a plurality of video streams, identifies a video encoding standard used for encoding video streams of the plurality of video streams, and interleaves portions of the plurality of video streams. A plurality of hardware decoding blocks perform operations associated with decoding the plurality of video streams, wherein different subsets of the plurality of hardware decoding blocks are for decoding video streams encoded using different video encoding standards, such that interleaved video streams are decoded by activating subsets of the plurality of hardware decoding blocks for use in decoding the plurality of video streams. A plurality of register sets store parameters associated with the plurality of video streams.

主权项

1. A hardware multi-stream multi-standard video decoder device comprising:
a command parser for accessing a plurality of video streams, for identifying a video encoding standard used for encoding video streams of said plurality of video streams, and for interleaving portions of said plurality of video streams; a plurality of hardware decoding blocks for performing operations associated with decoding said plurality of video streams, wherein different subsets of said plurality of hardware decoding blocks are for decoding video streams encoded using different video encoding standards, such that interleaved video streams are decoded by said command parser selectively activating and/or deactivating subsets of said plurality of hardware decoding blocks upon receipt of a video stream of said plurality of video streams during an initial stage for use in decoding said plurality of video streams responsive to said identified video encoding standard; and a plurality of register sets for storing parameters associated with said plurality of video streams, wherein each register set of said plurality of register sets is associated with a respective video stream of said plurality of video streams, wherein said plurality of video streams are concurrently decoded using said plurality of register sets, wherein said command parser is operable to deactivate one or more hardware decoding blocks that were previously activated based on the one or more hardware decoding blocks not being involved in decoding a portion of said plurality of video streams, and wherein said command parser is operable to deactivate hardware decoding blocks within a stage of a multiple stage macroblock level pipeline if no data of said plurality of video streams is received at said stage, and wherein the hardware multi-stream multi-standard video decoder device further comprises a hardware post-processing block for post-processing a decoded video stream, wherein said command parser is further configured to deactivate one or more of said plurality of hardware decoding blocks if a video stream of the plurality of video streams received at said command parser is a decoded video stream such that said hardware post-processing block performs said post-processing operation on said decoded video stream.