Method of fabricating a metal gate semiconductor device

摘要

A method of semiconductor device fabrication including providing a substrate having a gate dielectric layer such as a high-k dielectric disposed thereon. A tri-layer element is formed on the gate dielectric layer. The tri-layer element includes a first capping layer, a second capping layer, and a metal gate layer interposing the first and second capping layer. One of an nFET and a pFET gate structure are formed using the tri-layer element, for example, the second capping layer and the metal gate layer may form a work function layer for one of an nFET and a pFET device. The first capping layer may be a sacrificial layer used to pattern the metal gate layer.

主权项

1. A method, comprising:
providing a substrate; forming a third capping layer on the substrate; patterning the third capping layer; forming a gate dielectric layer on both the substrate and the patterned third capping layer; forming a tri-layer element on the gate dielectric layer, wherein the tri-layer element includes a first capping layer, a second capping layer, and a metal gate layer interposing the first and second capping layers; and forming at least one of an nFET and a pFET gate structure using the tri-layer element.