Shift register and gate driving circuit using the same

摘要

Disclosed are a shift register, and a gate driving circuit including a plurality of shift registers connected in sequence to respectively supply scan signals to a plurality of gate lines of a display device. Each shift register includes: an input unit which outputs a directional input signal having a gate high or low voltage based on an output signal from a previous or subsequent shift register to a first node; an inverter unit which is connected to the first node, generates an inverting signal to a signal at the first node, and outputs the inverting signal to a second node; and an output unit which includes a pull-up unit connected to the first node and activating an output clock signal based on the signal at the first node, and a pull-down unit activating and outputting a pull-down output signal based on a signal at the second node.

主权项

1. A gate driving circuit comprising a plurality of shift registers connected in sequence to respectively supply scan signals to a plurality of gate lines of a display device,
the shift register comprising: an input unit which outputs a directional input signal having a gate high voltage VGH or a gate low voltage VGL based on an output signal from a previous or subsequent shift register of the shift register to a first node; an inverter unit which is connected to the first node, generates an inverting signal to a signal at the first node, and outputs the inverting signal to a second node; and an output unit which comprises a pull up unit connected to the first node and activating an output clock signal based on the signal at the first node to be output as an output signal to a corresponding gate line, and a pull-down unit activating and outputting a pull-down output signal based on a signal at the second node, wherein the inverter unit is controlled by coupling with a control clock signal, wherein the inverter unit comprises: a first switching device that comprises a gate terminal to receive the control clock signal through a capacitor, a drain terminal to receive the control clock signal, and a source terminal connected to the second node; a second switching device that comprises a gate terminal connected to the first node, a drain terminal connected to the second node, and a source terminal connected to a base voltage terminal; and a third switching device that comprises a gate terminal connected to the first node, a drain terminal connected to the gate of the first switching device, and a source terminal connected to the base voltage terminal.