发明名称 Dummy metal gate structures to reduce dishing during chemical-mechanical polishing
摘要 The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect.
申请公布号 US9209182(B2) 申请公布日期 2015.12.08
申请号 US201313936909 申请日期 2013.07.08
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Chern Chan-Hong;Lin Chih-Chang;Chang Jacklyn;Tran Julie
分类号 H01L27/092;H01L27/02;H01L21/321;H01L21/8238 主分类号 H01L27/092
代理机构 Slater & Matsil, L.L.P. 代理人 Slater & Matsil, L.L.P.
主权项 1. A device, comprising: a plurality of analog device gate structures over an active area, wherein the analog device gate structures include respective metal gate layers; and a plurality of dummy gate structures, wherein a first dummy gate structure of the plurality of dummy gate structures is interjacent two neighboring analog device gate structures, wherein a first surface of the plurality of analog device gate structure is coplanar with a second surface of the plurality of dummy gate structures, wherein the two neighboring analog device gate structures overlap an isolation region, and wherein the first dummy gate structure is completely within the active area in a plan view.
地址 Hsin-Chu TW