发明名称 |
Semiconductor device having a multilayer interconnection structure |
摘要 |
A semiconductor device includes first and second conductor patterns embedded in a first interlayer insulation film and a third conductor pattern embedded in a second interlayer insulation film, the third conductor pattern including a main part and an extension part, the extension part being electrically connected to the first conductor pattern by a first via-plug, the extension part having a branched pattern closer to the main part compared with the first conductor pattern, the branched pattern making a contact with the second conductor pattern via a second via-plug, each of the main part, extension part including the branched pattern, first via-plug and second via-plug forming a damascene structure. |
申请公布号 |
US9209111(B2) |
申请公布日期 |
2015.12.08 |
申请号 |
US201414322491 |
申请日期 |
2014.07.02 |
申请人 |
FUJITSU SEMICONDUCTOR LIMITED |
发明人 |
Watanabe Kenichi;Nakamura Tomoji;Otsuka Satoshi |
分类号 |
H01L23/48;H01L23/522;H01L23/528;H01L23/532 |
主分类号 |
H01L23/48 |
代理机构 |
Fujitsu Patent Center |
代理人 |
Fujitsu Patent Center |
主权项 |
1. A semiconductor device comprising:
a substrate; a first conductor pattern and a second conductor pattern, that is separated from said first conductor pattern, formed above said substrate; a third conductor pattern formed above said first conductor pattern and said second conductor pattern; an extension part, that is narrower than said third conductor pattern, formed to extend in a layer identical to said third conductor pattern above said first conductor pattern and said second conductor pattern and connected to a first edge of said third conductor pattern in a plan view; a first via-plug formed on said first conductor pattern and under said extension part; a dummy extension part, that is narrower than said third conductor pattern, formed to extend in a layer identical to said third conductor pattern above said first conductor pattern and said second conductor pattern and connected to a first edge of said third conductor pattern in a plan view; and a second via-plug formed on said second conductor pattern under said dummy extension part. |
地址 |
Yokohama JP |