Conductor layout technique to reduce stress-induced void formations

摘要

A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. One or multiple notches are designed in the layout on a selective portion of the mask for patterning conductor line. The existence of the notch or notches on the selective portion generates extra stress components within the conductor line than would exist without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.

主权项

1. A method comprising: providing a mask including a plurality of mask lines including at least a first mask line including at least one notch shape;
fabricating a portion of a semiconductor circuit using the mask to form a plurality of conductive lines corresponding to the plurality of mask lines and including a first conductive line corresponding to the first mask line, the first conductive line including parallel edges extending in a lengthwise direction and having at least a first notch positioned at a first lengthwise location and a second notch positioned at a second lengthwise location that is different from the first lengthwise location on a first edge of said parallel edges, each of the first and second notches corresponding to a respective notch shape of the at least one notch shape, wherein the first conductive line is surrounded by an insulator material and interconnects at least two components of the semiconductor circuit and the fabricating results in formation of residual stresses within the plurality of conductive lines and the insulator material; and further fabricating further portions of the semiconductor circuit to produce the semiconductor circuit including to the first conductive line at the first lengthwise location between a first edge of the parallel edges and an innermost edge of the first notch and is aligned with the second notch in a widthwise direction, wherein the first and the second notch extend from the first edge of the first conductor line and a second parallel edge of said first conductor line is a substantially straight line that extends continuously between said first and second lengthwise locations, wherein each of the at least one first notch and the second notch generate extra stress components within the first conductive line compared to other conductive lines of the plurality of conductive lines and wherein the extra stress components substantially counteract the residual stresses.