Memory array with power-efficient read architecture

摘要

Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings can include a first string of memory cells and a second string of memory cells arranged substantially parallel and adjacent to one another. The lower strings can include a third string of memory cells and a fourth string of memory cells arranged substantially parallel and adjacent to one another. The strings can each have a separate sense amplifier coupled thereto. The first and third strings and the second and fourth strings can be configured to be respectively coupled in series with each other during a read operation. Additional apparatuses and methods are described.

主权项

1. An apparatus, comprising:
a first string of memory cells; and a second string of memory cells, the second string of memory cells being configured to receive at least a portion of a current flowing in the first string of memory cells during a read operation, the first string of memory cells and the second string of memory cells being coupled by a common node located therebetween.