发明名称 |
Vertical structure semiconductor memory devices and methods of manufacturing the same |
摘要 |
A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes. |
申请公布号 |
US9208885(B2) |
申请公布日期 |
2015.12.08 |
申请号 |
US201313920926 |
申请日期 |
2013.06.18 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Hwang Sung-Min;Kim Hansoo;Shim Sun-Il |
分类号 |
H01L27/088;G11C16/08;H01L27/115;H01L29/78;H01L23/48 |
主分类号 |
H01L27/088 |
代理机构 |
Harness, Dickey & Pierce, P.L.C. |
代理人 |
Harness, Dickey & Pierce, P.L.C. |
主权项 |
1. A semiconductor memory device comprising:
a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, the plurality of gate electrodes being separated from one another and being disposed along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from an impurity-doped second region of the substrate,
the substrate contact electrode extending from the substrate to a height greater than that of an uppermost gate electrode from among the plurality of gate electrodes; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes. |
地址 |
Gyeonggi-do KR |