On die jitter tolerance test

摘要

A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, θ. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various θ values.

主权项

1. A method for determining jitter tolerance, the method comprising:
generating an inverted signal having a phase shifted by approximately 180 degrees from a phase of a received input signal; generating a first phase shifted signal having a phase shifted by a first amount in a first direction relative to an edge of the inverted signal; generating a second phase shifted signal having a phase shifted by a second amount in a direction opposite to the first direction; detecting a value of the input signal at each of three distinct latch times corresponding to the edge of the inverted signal, an edge of the first phase shifted signal, and an edge of the second phase shifted signal; comparing each of the detected values of the input signal; and generating a result of the comparison, the result of the comparison indicative of a measure of jitter tolerance of the input signal.