Ratioless near-threshold level translator

摘要

An output circuit, between a first power supply terminal and a second power supply terminal, receives a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal and provides a second logic signal, complementary to the first logic signal. A level translator is in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential. The level translator is designed so that it may be implemented using a subset of the transistors that have the shortest channel length and narrowest channel width.

主权项

1. A circuit, comprising:
an output circuit (202, 302, 402) coupled between a first power supply terminal and a second power supply terminal that receives (IN1) a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal (VDD1) and a second logic state based on a voltage at the second power supply terminal (VSS1) and provides a second logic signal (IN2), complementary to the first logic signal, that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal; and a level translator, comprising:
a first transistor (214, 314, 416) of a first conductivity type having a first current electrode for receiving the first logic signal, a second current electrode, and a control electrode;a first transistor (208, 308, 422) of a second type having a first current electrode for receiving the first logic signal, a second current electrode coupled to the second current electrode of the first transistor of the first type, and a control electrode coupled to the second power supply terminal;a second transistor (206, 304, 406) of the second conductivity type having a control electrode that receives the first input signal, a first current electrode coupled to a third power supply terminal (VDD2, VSS2), and a second current electrode as a first output;a second transistor (212, 312, 412) of the first conductivity type having a control electrode for receiving the first logic signal;a third transistor (210, 310, 410) of the first conductivity type having a control electrode coupled to the second current electrode of the second transistor of the second conductivity type, wherein first and second current electrodes of the second and third transistors of the first conductivity type are coupled in series between a fourth power supply terminal and the second current electrode of the first transistor of the second conductivity type;a fourth transistor (204, 306, 404) of the first conductivity type having a control electrode coupled to the second current electrode of the first transistor of the second conductivity type, a first current electrode coupled to the second current electrode of the second transistor of the second conductivity type, and a second current electrode coupled to the fourth power supply terminal; andan inverting circuit (216, 316, 416) coupled to the third and fourth power supply terminals having an input coupled to the second current electrode of the second transistor of the second conductivity type and an output coupled to the control electrode of the first transistor of the first conductivity type.