发明名称 |
System and method for reading memory cells by accounting for inter-cell interference |
摘要 |
A system including a read module and a detector module. The read module is configured to generate a plurality of read signals by reading a plurality of memory cells located along a bit line or a word line. The detector module is configured to detect a sequence of data stored in the plurality of memory cells based on (i) the plurality of read signals, and (ii) a plurality of reference signals associated with the plurality of memory cells. One of the plurality of reference signals associated with a first memory cell of the plurality of memory cells includes one of a first signal and a second signal. The first signal is free of interference from a second memory cell adjacent to the first memory cell along the bit line or the word line. The second signal accounts for interference from the second memory cell. |
申请公布号 |
US9208882(B2) |
申请公布日期 |
2015.12.08 |
申请号 |
US201414257529 |
申请日期 |
2014.04.21 |
申请人 |
Marvell World Trade LTD. |
发明人 |
Yang Xueshi;Wu Zining |
分类号 |
G11C16/06;G11C16/04;G11C7/02;G11C16/26;G11C16/34;G11C7/14 |
主分类号 |
G11C16/06 |
代理机构 |
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代理人 |
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主权项 |
1. A system comprising:
a read module configured to generate a plurality of read signals by reading a plurality of memory cells located along a bit line or a word line; and a detector module configured to
detect a sequence of data stored in the plurality of memory cells based on (i) the plurality of read signals, and (ii) a plurality of reference signals associated with the plurality of memory cells,wherein one of the plurality of reference signals associated with a first memory cell of the plurality of memory cells includes one of a first signal and a second signal,wherein the first signal is free of interference from a second memory cell adjacent to the first memory cell along the bit line or the word line, andwherein the second signal accounts for interference from the second memory cell. |
地址 |
St Michael BB |