Semiconductor device and method of making

摘要

The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by concurrently formed metal-semiconductor compound contact regions at the source and drain and metal-semiconductor compounds in vias formed at positions corresponding to the source and drain. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the metal-semiconductor compounds in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the metal-semiconductor compound source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias.

主权项

1. A method of making a semiconductor device, comprising:
A. forming at least one transistor on a semiconductor substrate, each transistor having a source and a drain; B. forming an insulator layer covering the at least one transistor; C. etching the insulator layer to form vias at the source and drain of each transistor; and D. forming metal-silicide contact regions at the source and drain of each transistor, and forming metal-semiconductor compounds in the vias to lead out the source and drain; wherein steps B and C are performed before the metal-silicide contact regions are formed at the source and drain of each transistor; wherein the at least one transistor is formed on a semiconductor substrate and wherein step D comprises: D1-1. depositing a layer of silicon-containing semiconductor material over the insulator layer, the silicon-containing semiconductor material selected from the group consisting of silicon, silicon germanium (SiGe), and a silicon and silicon germanium Si/SiGe stacked structure, at least a portion of the silicon-containing semiconductor material is deposited in the vias; D1-2. depositing a layer of metal over the layer of silicon-containing semiconductor material; and D1-3. placing the substrate in a microwave heating chamber and performing annealing to cause metal-semiconductor compound to be formed at least in the vias, wherein multi-mode and multi-frequency microwaves are employed in the microwave heating chamber during annealing; and D1-4. removing any metal and metal-semiconductor compound outside of the vias by chemical mechanical polishing (CMP), while retaining metal-semiconductor compound formed in the vias; and wherein after step D1-1 and before step D1-2, the method further comprises removing any of the silicon-containing semiconductor material outside of the vias by chemical mechanical polishing (CMP).