SRAM well-tie with an uninterrupted grated first poly and first contact patterns in a bit cell array

摘要

An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in SRAM cells. Strap rows of the SRAM containing well ties and/or substrate taps which have SRAM cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps.

主权项

1. An integrated circuit, comprising:
a static random access memory (SRAM), comprising:
a strap row containing at least one of a well tie and a substrate tap;a first SRAM cell region adjacent to said strap row;a second SRAM cell region adjacent to said strap row opposite from said first SRAM cell region;a plurality of circuit elements disposed in said strap row, in said first SRAM cell region and in said second SRAM cell region, said circuit elements being configured in a periodic pattern of alternating lines and spaces, such that a difference between a pitch length of said circuit elements in said strap row and a pitch length of said circuit elements in said first SRAM cell region and in said second SRAM cell region is within 10 percent;a first half-cell row located between said strap row and said first SRAM cell region; anda second half-cell row located between said strap row and said second SRAM cell region.