Method and apparatus for delay compensation in data transmission

摘要

A method and apparatus for delay compensation in data transmission is disclosed. In one embodiment, an IC is configured to transmit data along with a clock signal to which the data is synchronized at the receiver. The IC includes a delay circuit configured to receive the data, which is transmitted in beats. The delay circuit includes a number of pipelines corresponding to the number of beats. Beats of data input into the delay circuit are routed to particular ones of the pipelines in accordance with a desired amount of delay. The delay applied to the data may be set to align the data with the clock signal at the receiver and to compensate for inherent delays that affect the clock signal.

主权项

1. An integrated circuit comprising:
clock generation circuitry configured to transmit a first clock signal, wherein the clock generation circuitry is configured to generate a plurality of clock signals including the first clock signal; a delay circuit configured to delay data transmitted with the first clock signal, the delay circuit comprising:
a plurality of staging flops, wherein each staging flop is configured to receive data corresponding to one of a plurality of beats;a plurality of pipelines each having a plurality of clocked storage circuits;a first plurality of selection circuits coupled between the plurality of staging flops and the plurality of pipelines, wherein the plurality of selection circuits are configured to route data from selected ones of the plurality of staging flops into correspondingly coupled ones of the plurality of pipelines, wherein an amount of delay applied to a given beat of data is dependent upon which of the plurality of pipelines to which it is routed; anda second plurality of selection circuits, wherein the second plurality of selection circuits is configured to select each of the pipelines in sequence to output one beat of data for each cycle of the first clock signal; wherein the clock generation circuitry is coupled to provide selected ones of the plurality of clock signals to corresponding ones of the plurality of clocked storage circuits in each of the plurality of pipelines.