发明名称 Clock selection system and method
摘要 The present invention systems and methods enable configuration of functional components in integrated circuits. In one embodiment clock signal selection system includes an arbitration component, a control component, and a selection component The arbitration component coordinates arbitration eligibility between a plurality of clock signals. The control component controls the coordination utilizing a clock signal from the plurality of clock signals. The selection component selects between the plurality of signals.
申请公布号 US9209792(B1) 申请公布日期 2015.12.08
申请号 US200711893500 申请日期 2007.08.15
申请人 NVIDIA CORPORATION 发明人 Browning Gary A.
分类号 H03K17/00;G06F1/08;G06F1/04;H03K19/173;H03K19/00;H03K5/15;H03K5/135 主分类号 H03K17/00
代理机构 代理人
主权项 1. A clock signal selection system comprising: an arbitration component for coordinating eligibility between a plurality of clock signals input to said arbitration component, wherein each one of the plurality of clock signals have a respective each one of a plurality of corresponding respective external clock selection indication signals input to said arbitration component, wherein at least two of said external clock selection indication signals are independently externally generated, wherein said arbitration component includes a one hot mechanism; a control component for controlling the coordination utilizing a clock signal from the plurality of clock signals, wherein a first one of the plurality of clock signals that is currently running is utilized for controlling the coordination and selection of a second one of the plurality of clock signals; and a selection component for selecting between the plurality of clock signals, wherein the selection component includes a multiplexer and the multiplexer includes: a clock gate for coordinating timing between a selection by the selection component and control component with a selected clock signal transition to avoid glitches; and an OR gate for logically ORing clock signal output.
地址 Santa Clara CA US