DDR retiming circuit

摘要

An integrated circuit receives a DDR (Double Data Rate) data signal and an associated DDR clock signal, and communicates those signals from integrated circuit input terminals a substantial distance across the integrated circuit to a subcircuit that then receives and uses the DDR data. Within the integrated circuit, a DDR retiming circuit receives the DDR data signal and the associated DDR clock signal from the terminals. The DDR retiming circuit splits the DDR data signal into two components, and then transmits those two components over the substantial distance toward the subcircuit. The subcircuit then recombines the two components back into a single DDR data signal and supplies the DDR data signal and the DDR clock signal to the subcircuit. The DDR data signal and the DDR clock signal are supplied to the subcircuit in such a way that setup and hold time requirements of the subcircuit are met.

主权项

1. An integrated circuit comprising:
a first input terminal that receives a double date rate (DDR) data signal onto the integrated circuit; a first input buffer; a second input terminal that receives a DDR clock signal onto the integrated circuit; a second input buffer; a first sequential logic element (SLE) having a data input lead and a data output lead, wherein the DDR data signal passes from the first input terminal, through the first input buffer, and to the data input lead of the first SLE; a second SLE having a data input lead and a data output lead, wherein the DDR data signal passes from the first input terminal, through the second input buffer, and to the data input lead of the second SLE; a first data signal path; a second data signal path; a third SLE having a data input lead and a data output lead, wherein the data input lead of the third SLE is coupled via the first data signal path to the data output lead of the first SLE; a fourth SLE having a data input lead and a data output lead, wherein the data input lead of the fourth SLE is coupled via the second data signal path to the data output lead of the second SLE; a multiplexer having first data input lead, a second data input lead, a select input lead, and a data output lead, wherein the first data input lead of the multiplexer is coupled to the data output lead of the third SLE, wherein the second data input lead of the multiplexer is coupled to the data output lead of the fourth SLE; and a DDR Clock Signal Supplying Circuit (DCSSC) having a first portion, a second portion, and a third portion, wherein the DDR clock signal passes from the second input terminal, through the second input buffer, through the first portion of the DCSSC, through the second portion of the DCSSC, and through the third portion of the DCSSC to the select input lead of the multiplexer, wherein clock input leads of the first and second SLEs are coupled to the first portion of the DCSSC such that the first SLE is clocked on rising edges of the DDR clock signal and the second SLE is clocked on falling edges of the DDR clock signal, and wherein clock input leads of the third and fourth SLEs are coupled to the third portion of the DCSSC such that the third SLE is clocked on falling edges of the DDR clock signal and the fourth SLE is clocked on rising edges of the DDR clock signal.