Universal test structures based SRAM on-chip parametric test module and methods of operating and testing

摘要

An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first and second UTS ports of the SRAM UTS for independent connection to first and second on-chip test pads, respectively. The integrated circuit OCP test structure further includes a UTS OCP router connected to the OCP controller and configured to connect the first and second UTS ports of the SRAM UTS to the first and second on-chip test pads, respectively. Methods of operating an integrated circuit OCP test structure and OCP testing of an integrated circuit are also included.

主权项

1. An integrated circuit, comprising:
a static random access memory (SRAM) containing a plurality of SRAM universal test structures (UTSs), each having more than two UTS ports; first and second on-chip test pads; multiplexer circuitry, coupled between the plurality of SRAM UTSs and the first and second on-chip test pads; UTS on-chip parametric (OCP) router circuitry, coupled in series with the multiplexer circuitry between the plurality of SRAM UTSs and the first and second on-chip test pads, the UTS OCP router circuitry for selectively coupling UTS ports to one of the first and second on-chip test pads, to a sourcing supply voltage, to a sinking supply voltage, or to electrically float; and an on-chip parametric (OCP) controller coupled to control the multiplexer circuitry to select one of the SRAM UTSs for coupling to the first and second of on-chip test pads, and coupled to the UTS OCP router circuitry to control the selective coupling of UTS ports to the first and second on-chip test pads, to a sourcing supply voltage, to a sinking supply voltage, or to electrically float.