Variable resistance memory with lattice array using enclosing transistors

摘要

A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.

主权项

1. A method of forming a memory array comprising:
forming a plurality of word lines over a substrate to form groups of at least three transistors, each group sharing one of a plurality of common source/drain regions; forming a phase change memory element electrically coupled to a common source/drain region shared by a first group of transistors; forming a bitline contact electrically coupled to a common source/drain region shared by a second group of transistors, wherein the common source/drain region coupled to the bitline contact is electrically coupled to the common/source drain region coupled to the phase change memory element through a transistor common to the first and second groups of transistors; and forming a top electrode select line electrically coupled to the phase change memory element, wherein forming the plurality of word lines further comprises:
forming a first plurality of isolated gate stacks along a first direction over the substrate, a second plurality of isolated gate stacks along a second direction over the substrate, and a third plurality of isolated gate stacks along a third direction over the substrate, wherein the first, second, and third directions comprise a hexagonal array pattern; andforming a first electrical connection between the first plurality of gate stacks to form the first plurality of word lines, a second electrical connection between the second plurality of gate stacks to form the second plurality of word lines, and a third electrical connection between the third plurality of gate stacks to form the third plurality of word lines.