Fin field effect transistor with dielectric isolation and anchored stressor elements

摘要

A first fin field effect transistor and a second fin field effect transistor are formed on an insulator layer overlying a semiconductor material layer. A first pair of trenches is formed through the insulator layer in regions in which a source region and a drain region of the first fin field effect transistor is to be formed. A second pair of trenches is formed partly into the insulator layer without extending to the top surface of the semiconductor material layer. The source region and the drain region of the first field effect transistor can be epitaxial stressor material portions that are anchored to, and epitaxially aligned to, the semiconductor material layer and apply stress to the channel of the first field effect transistor to enhance performance. The insulator layer provides electrical isolation from the semiconductor material layer to the second field effect transistor.

主权项

1. A semiconductor structure comprising:
a doped semiconductor layer located in a semiconductor substrate; an insulator layer located on a top surface of said doped semiconductor layer; a first semiconductor fin located on a first portion of a top surface of said insulator layer; a first gate stack straddling said first semiconductor fin; a first source region contacting a first end wall of said first semiconductor fin and said doped semiconductor layer and extending through said insulator layer; a first drain region contacting a second end wall of said first semiconductor fin and said doped semiconductor layer, spaced from said first source region, and extending through said insulator layer; a second semiconductor fin located on a second portion of said top surface of said insulator layer; a second gate stack straddling said second semiconductor fin; a second source region contacting a first end wall of said second semiconductor fin and vertically spaced from said semiconductor substrate by said insulator layer; and a second drain region contacting a second end wall of said second semiconductor fin and vertically spaced from said semiconductor substrate by said insulator layer.