Manufacturing method of a semiconductor device and method for creating a layout thereof

摘要

A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

主权项

1. A method for manufacturing a semiconductor device comprising:
forming an insulation layer to be processed over a semiconductor substrate; forming a first sacrificial layer in a first area over the insulation layer, the first sacrificial layer being patterned to form a first plurality of functioning wirings in a first subarea of the first area, a second plurality of functioning wirings in a second subarea of the first area, a third plurality of functioning wirings in a third subarea of the first area, and a fourth plurality of functioning wirings in a fourth subarea of the first area, the first plurality of functioning wirings including a first functioning wiring having a side wall facing an outside of the first subarea, the second plurality of functioning wirings including a second functioning wiring having a side wall facing an outside of the second subarea, the third plurality of functioning wirings including a third functioning wiring having a side wall facing an outside of the third subarea, the fourth plurality of functioning wirings including a first functioning wiring having a side wall facing an outside of the fourth subarea, the first functioning wiring, the second functioning wiring, the third functioning wiring, and the fourth functioning wiring being parallel; forming a second sacrificial layer in a second area over the insulation layer, the second sacrificial layer being patterned to form a plurality of dummy wirings in a fifth subarea of the second area, and a sixth subarea of the second area, the fifth subarea being arranged between the first functioning wiring and the second functioning wiring, the sixth subarea being arranged between the third functioning wiring and the fourth functioning wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity to form the first plurality of functioning wirings, the second plurality of functioning wirings, the third plurality of functioning wirings, the fourth plurality of functioning wirings, and the plurality of dummy wirings, each functioning wiring in the first plurality of functioning wirings being parallel to and separated by a first distance from an adjacent wiring in the first plurality of functioning wirings, each functioning wiring in the second plurality of functioning wirings being parallel to and separated by the first distance from an adjacent wiring in the second plurality of functioning wirings, each functioning wiring in the third plurality of functioning wirings being parallel to and separated by a second distance from an adjacent wiring in the third plurality of functioning wirings, each functioning wiring in the fourth plurality of functioning wirings being parallel to and separated by the second distance from an adjacent wiring in the fourth plurality of functioning wirings.