Metal replacement process for low resistance source contacts in 3D NAND

摘要

A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to memory holes at a bottom of a stack. The stack includes alternating control gate layers and dielectric layers on a substrate, and memory holes are etched through the stack. The process avoids the need to etch through films at the bottom of the memory hole. Instead, a path is formed from the bottom of the memory hole to the top of the stack. The path includes a horizontal portion using a voided trench in a substrate dielectric, and a passageway etched in the stack. The memory films, a channel material and a dielectric material are deposited throughout the interior surfaces of the void and the memory holes concurrently. The path is filled with metal to form a continuous, low resistance conductive path.

主权项

1. A method for fabricating a 3d stacked non-volatile memory device, comprising:
forming a memory hole in a stack, the stack comprising alternating control gate layers and dielectric layers on a substrate dielectric; forming a void in the substrate dielectric, a bottom of the memory hole is connected to the void; forming a passageway in the stack between a top of the stack and the void; depositing a plurality of materials in the void and the memory hole, the plurality of materials comprise a programmable material, a channel material and a dielectric material; removing a portion of the dielectric material which is in the void, exposing a portion of the channel material which is in the void; doping the portion of the channel material which is in the void, the doping comprises introducing a dopant to the void via the passageway; and depositing a metal in the void and the passageway, the metal extends to the bottom of the memory hole.