| 发明名称 | Timing violation handling in a synchronous interface memory | ||
| 摘要 | A phase-change memory includes a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, where an activate command starts and following activate commands are ignored until a preset time has elapsed. | ||
| 申请公布号 | US9208835(B2) | 申请公布日期 | 2015.12.08 |
| 申请号 | US200913518371 | 申请日期 | 2009.12.29 |
| 申请人 | Micron Technology, Inc. | 发明人 | Ferrario Marco;Laurent Christophe Vincent Antoine;Mastroianni Francesco |
| 分类号 | G11C7/10;G11C7/22;G11C8/18;G11C13/00;G11C11/21;G06F12/08 | 主分类号 | G11C7/10 |
| 代理机构 | Schwegman Lundberg & Woessner, P.A. | 代理人 | Schwegman Lundberg & Woessner, P.A. |
| 主权项 | 1. A Phase-Change Memory (PCM) device to output data in a three phase address read, comprising: a PREACTIVE phase to provide an upper row address of a row address from a Row Address Buffer (RAB) for the PCM device, the row address being different from a bank address in the device; an ACTIVATE phase to combine the upper row address with a lower row address of the row address to select PCM data for a Row Data Buffer; and a READ phase to output the PCM data from the Row Data Buffer, where an Activate command starts and following Activate commands are ignored until a preset time has elapsed. | ||
| 地址 | Boise ID US | ||