Semiconductor structure and method for manufacturing the same

摘要

A method for manufacturing a semiconductor structure comprises following steps: providing an SOI substrate, forming a gate stack on the SOI substrate, forming sidewall spacers on sidewalls of the gate stack, and forming source/drain regions on each side of the gate stack; depositing a first metal layer on surfaces of an entire semiconductor structure, and then removing the first metal layer; forming an amorphous semiconductor layer on surfaces of the source/drain regions; depositing a second metal layer on surfaces of the entire semiconductor structure, and then removing the second metal layer; and annealing the semiconductor structure. Accordingly, the present invention further provides a semiconductor structure. The present invention is capable of effectively reducing contact resistance at source/drain regions.

主权项

1. A method of manufacturing a semiconductor structure, comprising:
a) providing an SOI substrate, forming a gate stack on the SOI substrate, forming sidewall spacers on sidewalls of the gate stack, and forming source/drain regions on each side of the gate stack; b) depositing a first metal layer on surfaces of the entire semiconductor structure, and then removing the first metal layer before any annealing, wherein some of the first metal layer has come into source/drain regions during formation of the first metal layer; c) depositing an amorphous semiconductor layer to cover the semiconductor structure; doping the amorphous semiconductor layer; removing a part of the amorphous semiconductor layer, and keeping the amorphous semiconductor layer on surfaces of the source/drain regions; d) depositing a second metal layer on surfaces of an entire semiconductor structure, and then removing the second metal layer before any annealing, wherein some of the second metal layer has come into the amorphous silicon layers after the second metal layer is removed; e) annealing the semiconductor structure to form a first contact layer on surfaces of the source/drain regions and second contact layers are formed on the upper surface of each amorphous semiconductor layers on surfaces of the source/drain regions and some of the amorphous semiconductor layer remains between the first metal silicide layer and the second metal silicide layer after the annealing; wherein step b) occurs before step c) and e).