Weak bit compensation for static random access memory

摘要

A static random access memory (SRAM) is provided. The SRAM includes a data line, a data line bar, and a current path block. The current path block includes at least two transistors configured to provide a current path for the data line in transition from a first logic voltage to a second logic voltage, wherein the current path block is connected to the data line and the data line bar during an entire duration of operation of the SRAM.

主权项

1. A static random access memory (SRAM), comprising:
a data line; a data line bar; and a current path block including at least two transistors configured to provide a current path for the data line in transition from a first logic voltage to a second logic voltage, a gate of a first transistor of the at least two transistors is connected to the data line bar, wherein the current path block is electrically connected to the data line and the data line bar during an entire duration of operation of the SRAM, the entire duration of operation of the SRAM including time periods where a memory cell associated with the current path block is not selected, and a gate of a second transistor of the at least two transistors is connected to a word line and is configured to receive a word line signal or a first pulse signal.