Internal address generation circuits

摘要

Internal address generation circuits are provided. The internal address generation circuit includes an aging detector and an address decoder. The aging detector generates an aging signal enabled when the number of times that an internal command signal for accessing memory cells is inputted is equal to or more than a reference number. The address decoder decodes an address signal in response to the aging signal to generate an internal address signal.

主权项

1. An internal address generation circuit, the circuit comprising:
an aging detector suitable for generating an aging signal enabled when the number of times that an internal command signal for accessing memory cells is inputted is equal to or more than a reference number; and an address decoder suitable for decoding an address signal in response to the aging signal to generate an internal address signal, wherein the internal address signal includes a first internal address signal and a second internal address signal, wherein when the aging signal is disabled, the address decoder decodes the address signal having a first level combination to generate the first internal address signal enabled and decodes the address signal having a second level combination to generate the second internal address signal enabled, and wherein when the aging signal is enabled, the address decoder decodes the address signal having the first level combination to generate the second internal address signal enabled and decodes the address signal having the second level combination to generate the first internal address signal enabled.