发明名称 INFORMATION PROCESSOR AND BUS CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To prevent decrease of performance due to bus contention.SOLUTION: The information processor includes: plural memories; and plural buses each connected to the plural memories. The information processor changes a logical address of the memory area and mapping of a physical address which is used by an input/output device, and transfers the access of the input/output device to any one of the plural buses on the basis of the mapping.
申请公布号 JP2015219810(A) 申请公布日期 2015.12.07
申请号 JP20140104264 申请日期 2014.05.20
申请人 FUJITSU LTD 发明人 SAKURAI HIROSHI
分类号 G06F13/14;G06F13/36 主分类号 G06F13/14
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