| 发明名称 |
SPLIT GATE MEMORY CELL WITH IMPROVED ERASE PERFORMANCE |
| 摘要 |
A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer. |
| 申请公布号 |
US2015349142(A1) |
申请公布日期 |
2015.12.03 |
| 申请号 |
US201414288975 |
申请日期 |
2014.05.28 |
| 申请人 |
WINSTEAD BRIAN A.;Chang Ko-Min;Swift Craig T. |
发明人 |
WINSTEAD BRIAN A.;Chang Ko-Min;Swift Craig T. |
| 分类号 |
H01L29/792;H01L29/51;H01L21/28;G11C16/14 |
主分类号 |
H01L29/792 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor device comprising:
a semiconductor substrate; a charge storage stack over a portion of the substrate, the charge storage stack including:
a first dielectric layer;a layer of nanocrystals in contact with the first dielectric layer;a second dielectric layer over and in contact with the layer of nanocrystals;a nitride layer over and in contact with the second dielectric layer; anda third dielectric layer over the nitride layer. |
| 地址 |
Bridgetown CA |
