VERTICAL BJT FOR HIGH DENSITY MEMORY

摘要

Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.

主权项

1. A method, comprising:
forming a collector region, which has a first conductivity type, in a semiconductor substrate; forming a base region, which has a second conductivity type opposite the first conductivity type, in the semiconductor substrate and abutting a top portion of the collector region; forming a conductive electrode over the base region, the conductive electrode extending over an upper surface of the semiconductor substrate and being electrically coupled to the base region; forming first and second emitter structures in the semiconductor substrate on opposite sides of the conductive electrode, the first and second emitter structures having the first conductivity type and abutting the base region; forming first and second contacts that are coupled to upper portions of the first and second emitter structures, respectively; and forming first and second data storage elements over the first and second contacts, wherein the first and second data storage elements are coupled to upper portions of the first and second contacts, respectively.