Methods and Apparatus for Artificial Exciton in CMOS Processes

摘要

Methods and apparatus for artificial exciton devices. An artificial exciton device includes a semiconductor substrate; at least one well region doped to a first conductivity type in a portion of the semiconductor substrate; a channel region in a central portion of the well region; a cathode region in the well region doped to a second conductivity type; an anode region in the well region doped to the first conductivity type; a first lightly doped drain region disposed between the cathode region and the channel region doped to the first conductivity type; a second lightly doped drain region disposed between the anode region and the channel region doped to the second conductivity type; and a gate structure overlying the channel region, the gate structure comprising a gate dielectric layer lying over the channel region and a gate conductor material overlying the gate dielectric. Methods are disclosed.

主权项

1. An artificial exciton device, comprising:
a semiconductor substrate; at least one well region in a portion of the semiconductor substrate and doped to a first conductivity type; isolation structures at a surface of the semiconductor substrate and positioned at a periphery of the at least one well region; a gate structure disposed on a surface of the semiconductor substrate and overlying the channel region, the gate structure comprising a gate dielectric layer lying over the channel region and a gate conductor material overlying the gate dielectric; a channel region defined at the surface of the semiconductor substrate in a central portion of the well region underlying the gate structure; a cathode region in the well region disposed spaced from one side of the channel region and doped to a second conductivity type opposite the first conductivity type; an anode region in the well region spaced from the channel region on a side opposite the cathode region, the anode region doped to the first conductivity type; a first lightly doped drain region in the at least one well region and disposed between the cathode region and the channel region, the first lightly doped drain region doped to the first conductivity type; and a second lightly doped drain region in the at least one well region and disposed between the anode region and the channel region, the second lightly doped drain region doped to the second conductivity type.