NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME

摘要

Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

主权项

1. A method
of erasing a nonvolatile memory device which includes a plurality of memory cell strings including a first memory cell string, the first memory cell string including a first string selection transistor connected to a bit-line, a first ground selection transistor and a first plurality of memory cells, the first plurality of memory cells being connected in series between the first string selection transistor and the first ground selection transistor, the plurality of memory cell strings being connected to a common source line, the method comprising: applying to a substrate an erase voltage that has a first level; applying a first voltage to a first ground selection line connected to the first ground selection transistor that is included in the first memory cell string and is connected to the first plurality of memory cells, the first ground selection transistor being formed on the substrate, the first plurality of memory cells being stacked on or above the substrate at a direction that is substantially vertical to the substrate; increasing the erase voltage from the first level to a second level higher than the first level during the applying the first voltage to the first ground selection line; floating the first ground selection line after a level of the erase voltage reaches to the second level; increasing the erase voltage from the second level to a third level higher than the second level during the floating the first ground selection line; and applying a plurality of word-line voltages to a plurality of word-lines connected to the first plurality of memory cells while the erase voltage increases from the first level to the third level, a level of each of the plurality of word-line voltages being determined based on a distance between the substrate and each of the plurality of word-lines, wherein the first memory cell string includes a channel hole having diameters corresponding to the first plurality of memory cells, the diameters being varied according to distances between the substrate and the first plurality of memory cells, and the first memory cell string includes a first dummy cell disposed between the first ground selection transistor and the first plurality of memory cells.