METHOD FOR IMPROVING SENSING MARGIN OF RESISTIVE MEMORY

摘要

A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line to operate in parallel as a merged memory cell; programming the resistance of the merged memory cell in response to the write data, the resistance of the two or more resistive memory cells in the merged memory cell being programmed simultaneously; and reading the programmed resistance value of the merged memory cell, the programmed resistance of the two or more memory cells in the merged memory cell being read simultaneously.

主权项

1. A resistive memory device, comprising:
a two-dimensional array of resistive memory cells, each memory cell being accessed by a word line, a bit line and a source line, resistive memory cells sharing a common word line forming a row of the array and resistive memory cells sharing a common bit line and a common source line forming a column of the array; a write driver configured to apply write bias voltages to the bit line and the source line to write data to one or more resistive memory cells in the array selected for access, the write bias voltages being applied to program a resistance of the one or more selected resistive memory cells in response to the write data; and a sense amplifier configured to sense a signal difference between a reference signal and a sense node signal and to generate an output signal indicative of the signal difference, the sense node signal being related to a programmed resistance of one or more resistive memory cells in the array selected for access, wherein two or more memory cells in a column of the array sharing the same bit line and the same source line are configured to operate in parallel as a merged memory cell, the write driver being configured to program the resistance of the two or more resistive memory cells in the merged memory cell simultaneously, and the sense amplifier being configured to read the programmed resistance of the two or more resistive memory cells in the merged memory cell simultaneously.