发明名称 INDIVIDUALLY READ-ACCESSIBLE TWIN MEMORY CELLS
摘要 The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell.
申请公布号 US2015348981(A1) 申请公布日期 2015.12.03
申请号 US201514671606 申请日期 2015.03.27
申请人 STMicroelectronics (Rousset) SAS 发明人 La Rosa Francesco;Niel Stephan;Regnier Arnaud
分类号 H01L27/115;G11C16/26;H01L29/788;H01L21/28;H01L29/06;H01L23/528;H01L29/423;G11C16/14;H01L29/66 主分类号 H01L27/115
代理机构 代理人
主权项 1. A non-volatile memory on a semiconductor substrate, comprising: a first memory cell including a first floating-gate transistor and a select transistor electrically coupled to each other, the select transistor having a vertical control gate embedded in the substrate and a vertical channel region extending along a first face of the embedded vertical control gate, a second memory cell including a first floating-gate transistor and a select transistor electrically coupled to each other, the select transistor sharing the control gate of the select transistor of the first memory cell and having a vertical channel region that extends along a second face of the embedded vertical control gate that is on an opposite side of the control gate with respect to the first face, a first bit line electrically coupled to the first floating-gate transistor of the first memory cell, a second bit line electrically coupled to the first floating-gate transistor of the second memory cell, a first control gate line electrically coupled to a control gate of the first floating-gate transistor of the first memory cell, and a second control gate line electrically coupled to a control gate of the first floating-gate transistor of the second memory cell.
地址 Rousset FR