DRAM CONTROLLER FOR VARIABLE REFRESH OPERATION TIMING

摘要

A method for selection of a DRAM refresh timing in a DRAM memory system is disclosed. The method may include running a workload for a first number of refresh intervals using a first DRAM refresh timing and making a first workload throughput measurement for the first number of refresh intervals. The method may also include running the workload for a second number of refresh intervals using a second DRAM refresh timing and making a second workload throughput measurement for the second number of refresh intervals. The method may further include deciding if the first throughput measurement is greater than the second throughput measurement, and then selecting the first DRAM refresh timing as a selected DRAM refresh timing, or deciding if the second throughput measurement is greater than the first throughput measurement, then selecting the second DRAM refresh timing as the selected DRAM refresh timing.

主权项

1. A memory controller to monitor and manage the throughput of a dynamic application workload running on a dynamic random-access memory (DRAM) system by periodically adjusting a DRAM refresh timing granularity that includes the duration of a DRAM refresh interval, the memory controller comprising:
a refresh mode controller (RMC) electrically coupled to the memory performance measurement unit (MPMU) and to the command scheduler, the RMC having registers to hold DRAM refresh mode information including a duration of a DRAM refresh interval, the RMC further having circuits to receive aggregated dynamic application workload throughput information sent from a MPMU, and to, in response, select and send, to a command scheduler, DRAM refresh mode information corresponding to a highest throughput measurement from the aggregated throughput information; an MPMU, electrically coupled to receive dynamic application workload throughput information from each of a command scheduler, a transaction queue and a memory bus, the MPMU having circuits to make, during the execution of a dynamic application workload, dynamic application workload throughput measurements based upon a received dynamic application workload throughput information and to combine the measurements into aggregated dynamic application workload throughput information; and a command scheduler, electrically coupled to the RMC and to the transaction queue, the command scheduler having circuits to receive refresh mode information from the RMC, and to generate and place memory commands within the transaction queue.