| 发明名称 |
Cell-Level Signal Electromigration |
| 摘要 |
A circuit design system includes a simulator that determines an average charging current provided by each current insertion point in a cell and an average charging current along a path in the cell between a reference pin position and a candidate pin position. A candidate pin placement tester updates the average charging current along the path by adding the average charging current of each insertion point to the average charging current along the path to produce an updated average charging current along the path and uses the updated average charging current along the path to determine a time to failure for the cell. |
| 申请公布号 |
US2015347665(A1) |
申请公布日期 |
2015.12.03 |
| 申请号 |
US201414292215 |
申请日期 |
2014.05.30 |
| 申请人 |
Jain Palkesh;Posser Gracieli;Reis Ricardo;Regents of the University of Minnesota |
发明人 |
Sapatnekar Sachin S.;Mishra Vivek;Jain Palkesh;Posser Gracieli;Reis Ricardo |
| 分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A circuit design system comprising:
a simulator that determines an average charging current provided by each current insertion point in a cell and an average charging current along a path in the cell between a reference pin position and a candidate pin position; a candidate pin placement tester that updates the average charging current along the path by adding the average charging current of each insertion point to the average charging current along the path to produce an updated average charging current along the path and using the updated average charging current along the path to determine a performance parameter value for the cell. |
| 地址 |
Bangalore IN |
