主权项 |
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor each including a gate, a source, and a drain; and a first wiring, a second wiring, and a third wiring, wherein the gate of the first transistor is electrically connected to the first wiring, one of the source and the drain of the first transistor is electrically connected to the second wiring, and the other of the source and the drain of the first transistor is electrically connected to a first node, wherein the gate of the second transistor is electrically connected to the first node, one of the source and the drain of the second transistor is electrically connected to the second wiring, and the other of the source and the drain of the second transistor is electrically connected to a second node, wherein the gate of the third transistor is electrically connected to the second node, one of the source and the drain of the third transistor is electrically connected to the first node, and the other of the source and the drain of the third transistor is electrically connected to a third node, wherein the gate of the fourth transistor is electrically connected to the third node, one of the source and the drain of the fourth transistor is electrically connected to the second node, and the other of the source and the drain of the fourth transistor is electrically connected to the third wiring, wherein the gate of the fifth transistor is electrically connected to the third node, one of the source and the drain of the fifth transistor is electrically connected to the third node, and the other of the source and the drain of the fifth transistor is electrically connected to the third wiring, wherein the first transistor further comprises:
an oxide semiconductor layer, the oxide semiconductor layer electrically connected to the source and the drain; anda gate insulating layer over the oxide semiconductor layer, the source, and the drain, wherein the gate is positioned over the gate insulating layer and overlaps with the oxide semiconductor layer, and wherein a bottom surface of the gate is positioned below a bottom surface of the oxide semiconductor layer. |