MEMORY ARRAY WITH A PAIR OF MEMORY-CELL STRINGS TO A SINGLE CONDUCTIVE PILLAR

摘要

An array of memory cells has a conductive pillar and a plurality of first and second memory cells coupled in series by the conductive pillar. Each first memory cell has a respective portion of a first charge trap adjacent to the conductive pillar and a respective first control gate adjacent to the respective portion of the first charge trap. Each second memory cell has a respective portion of a second charge trap adjacent to the conductive pillar and a respective second control gate adjacent to the respective portion of the second charge trap. Each first control gate is electrically isolated from each second control gate. A single select transistor may selectively couple the plurality of first memory cells and the plurality of second memory cells to one of a source line and a data line.

主权项

1. A memory array, comprising:
a plurality of series-coupled first memory cells, each first memory cell curving around a first curved side of a substantially vertical pillar and terminating at an isolation region; a plurality of series-coupled second memory cells, each second memory cell curving around a second curved side of the substantially vertical pillar and terminating at the isolation region; wherein respective ones of the first memory cells of the plurality of series-coupled first memory cells are respectively at same vertical levels as respective ones of the second memory cells of the plurality of series-coupled second memory cells.