| 发明名称 |
FET CHIP |
| 摘要 |
<p>An FET chip is configured to include an oscillation suppression circuit that has a gate capacitance C formed between a gate electrode 5c and two-dimensional electron gas, and a channel resistance R between the gate electrode 5c and a source electrode 7c, and therefore the oscillation suppression circuit is loaded by only an FET process to make an MMIC design unnecessary, so that it is possible to attain stabilization of an FET while suppressing increase in cost, and to suppress oscillation.</p> |
| 申请公布号 |
EP2843691(A4) |
申请公布日期 |
2015.12.02 |
| 申请号 |
EP20120875369 |
申请日期 |
2012.04.27 |
| 申请人 |
MITSUBISHI ELECTRIC CORPORATION |
发明人 |
OTSUKA, HIROSHI;OISHI, TOSHIYUKI;KUWATA, EIGO;YAMASAKI, TAKASHI;KIMURA, MAKOTO;NAKAYAMA, MASATOSHI |
| 分类号 |
H01L21/338;H01L21/822;H01L21/8232;H01L27/06;H01L27/07;H01L27/088;H01L27/095;H01L29/06;H01L29/20;H01L29/778;H01L29/812;H03F3/195 |
主分类号 |
H01L21/338 |
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