发明名称 分数クロック信号を生成するための技術
摘要 A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.
申请公布号 JP5827354(B2) 申请公布日期 2015.12.02
申请号 JP20140030247 申请日期 2014.02.20
申请人 アルテラ コーポレイションAltera Corporation 发明人 ティム トリ ホアン;ウィルソン ウォン;セルゲイ シュマライェフ
分类号 H03L7/197;H03L7/08;H03L7/183 主分类号 H03L7/197
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