发明名称 PLL回路
摘要 <P>PROBLEM TO BE SOLVED: To provide a PLL circuit which can properly and automatically set specification of a noise filter circuit. <P>SOLUTION: The PLL circuit includes: a filter circuit which performs filter processing to a first clock signal to generate a second clock signal; a phase comparator circuit which generates a control signal according to a phase comparison result between the second clock signal and a third clock signal; and an oscillation circuit including at least a first delay circuit which brings signal delay according to a value of the control signal to oscillate the third clock signal according to the signal delay, wherein the filter circuit includes a second delay circuit with the same configuration as that of the first delay circuit to bring the signal delay according to the value of the control signal, performs the filter processing to the first clock signal by the second delay circuit to generate the second clock signal. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP5827787(B2) 申请公布日期 2015.12.02
申请号 JP20100044211 申请日期 2010.03.01
申请人 スパンション エルエルシー 发明人 松並 弘幸
分类号 H03L7/08 主分类号 H03L7/08
代理机构 代理人
主权项
地址