延迟线电路及半导体积体电路;DELAY LINE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

一种延迟线电路，包括串联连接的精调延迟单元及粗调延迟单元。在精调延迟单元中，并联耦接于电源电压以及第一PMOS电晶体的源极之间的复数第二PMOS电晶体的闸极特征的宽度相等。耦接于电源电压以及第一PMOS电晶体的源极之间的至少一第三PMOS电晶体的闸极特征的宽度小于该些第二PMOS电晶体的闸极特征的宽度。并联耦接于接地电压以及第一NMOS电晶体的源极之间的复数第二NMOS电晶体的闸极特征的宽度相等。耦接于接地电压以及第一NMOS电晶体的源极之间的至少一第三NMOS电晶体的闸极特征的宽度小于该些第二NMOS电晶体的闸极特征的宽度。; and a plurality of coarse delay units coupled to the fine delay unit in series. In the fine delay unit, widths of gate features of a plurality of second PMOS transistors coupled between a power voltage and a source of a first PMOS transistor are equal. A width of a gate feature of at least one third PMOS transistor coupled between the power voltage and the source of the first PMOS transistor is smaller than the widths of the gate features of the second PMOS transistors. Widths of gate features of a plurality of second NMOS transistors coupled between a ground voltage and a source of a first NMOS transistor are equal. A width of a gate feature of at least one third NMOS transistor coupled between the ground voltage and the source of the first NMOS transistor is smaller than the widths of the gate features of the second NMOS transistors.