| 发明名称 | Low-power internal clock gated cell and method | ||
| 摘要 | A circuit includes a clock trigger block and a logic circuit. The logic circuit is configured to output a signal to the clock trigger block based on a logic level of an enable signal received at the logic circuit. The clock trigger block is configured to output an output signal response to a clock signal received at the clock trigger block and the signal received from the logic circuit. | ||
| 申请公布号 | US9203405(B2) | 申请公布日期 | 2015.12.01 |
| 申请号 | US201414277896 | 申请日期 | 2014.05.15 |
| 申请人 | Taiwan Semiconductor Manufacturing Co., Ltd. | 发明人 | Liu Chi-Lin;Hsieh Shang-Chih;Lu Lee-Chung;Wang Meng-Hsueh;Wu Chang-Yu |
| 分类号 | G06F1/04;H03K19/00;H03K3/033 | 主分类号 | G06F1/04 |
| 代理机构 | Duane Morris LLP | 代理人 | Duane Morris LLP |
| 主权项 | 1. A circuit, comprising: a clock trigger block configured to receive a clock signal; and a logic circuit configured to output a signal to the clock trigger block based on a logic level of an enable signal received at the logic circuit, wherein the clock trigger block is configured to output an output signal in response to the clock signal and the signal received from the logic circuit, and wherein the logic circuit includes a plurality of transistors, and when the circuit is not enabled in response to the logic level of the enable signal, at least one but fewer than one half of the plurality of transistors toggle in response to the clock signal. | ||
| 地址 | Hsin-Chu TW | ||