Lower power assembler

摘要

A method for processing data using a time-stationary multiple-instruction word processing apparatus, arranged to execute a plurality of instructions in parallel, said method comprising the following steps: generating a set of multiple-instruction words (INS(i), INS(i+1), INS(i+2)), wherein each multiple-instruction word comprises a plurality of instruction fields, wherein each instruction field encodes control information for a corresponding resource of the processing apparatus, and wherein bit changes between an instruction field related to a no-operation instruction, and a corresponding instruction field of an adjacent multiple-instruction word are minimised; storing input data in a register file (RF0, RF1); processing data retrieved from the register file based on control information derived from the set of multiple-instruction words; disabling the write back of result data to the register file during execution of a no-operation instruction using a first dedicated no-operation code (ws00, ws10, wp00, wp10).

主权项

1. A method for processing data using a time-stationary multiple-instruction word processing apparatus, arranged to execute a plurality of instructions in parallel, said method comprising the following steps:
generating a set of multiple-instruction words, wherein each multiple-instruction word comprises a plurality of instruction fields, wherein each instruction field encodes control information for a corresponding resource of the processing apparatus, and wherein bit changes between an instruction field related to a no-operation instruction, and a corresponding instruction field of an adjacent multiple-instruction word are minimized; storing input data in a register file; processing data retrieved from the register file based on control information derived from the set of multiple-instruction words; and disabling the write back of result data to the register file during execution of a no-operation instruction using a first dedicated no-operation code.