High speed read access memory array with variation tolerant bypass scheme with protection circuit

摘要

A memory array for process variation tolerant bypass operation. The memory array may utilize normal read operation data path of a memory I/O module. Accordingly, the speed at which the bypass operation may be executed may be increased. Furthermore, a potential for false read operations introduced by the utilization of the normal read operation data path of the memory I/O module may be reduced using a protect mechanism operable to block the output of false reads from the memory array.

主权项

1. A method for process variation tolerant bypass operation of a memory array, comprising:
receiving a memory command at the memory array corresponding to bypass operation of the memory array, wherein the memory command includes bypass data to be written to and read from a memory location of the memory array in a single clock cycle period of the memory array; writing, using a memory I/O module, the bypass data to a location in the memory array during the single clock cycle period; reading, using the memory I/O module, output data from the location in the memory array during the single clock cycle period; comparing the output data from the memory array during the single clock cycle period in relation to a bypass verification signal corresponding to an expected value of the output data of the single clock cycle period in view of the bypass data to determine whether the output data corresponds with the bypass data; and selectively passing the output data based on the comparing.