Systems and methods for monitoring LCD display panel resistance

摘要

Systems and methods for monitoring internal resistance of a display may include supplying the display via a capacitor with a first voltage and a second voltage configured to enable the display to receive touch inputs and display image data, respectively. The method may discharge the capacitor at least three times via a first resistor, a second resistor, and the first resistor and second resistor coupled in parallel with each other. The method may monitor three discharge waveforms that corresponds to when the capacitor discharges from the first voltage to the second voltage via the first resistor, the second resistor, and the first resistor and second resistor coupled in parallel with each other. Based at least in part on the discharge waveforms, the method may determine a chip on glass resistance value and a flex on glass resistance value that correspond to an internal resistance of the display.

主权项

1. A display driver circuit comprising:
a capacitor configured to provide a plurality of voltages to a display via a supply rail, wherein the capacitor is coupled in series with a chip on glass (COG) circuit and a flex on glass (FOG) circuit of the display; a plurality of resistors, wherein each of the plurality of resistors has substantially the same resistance value and wherein at least one of the plurality of resistors is associated with a matching error;
a plurality of switches configured to couple to the plurality of resistors, wherein each switch is configured to couple the capacitor to ground via a respective resistor of the plurality of resistors when closed, and wherein each resistor value of the plurality of resistors is associated with a different display manufacturer, one of which is the manufacturer of the display; andan interface configured to communicate with a processor, wherein the interface is configured to measure a sum of a COG resistance value and a FOG resistance value by: closing a first switch of the plurality of switches, thereby discharging the capacitor via a first resistor; measuring a first amount of time between when the capacitor has a first voltage value and when the capacitor discharges to a second voltage value via the first resistor; opening the first switch after the capacitor discharges to the second voltage value; closing a second switch of the plurality of switches, thereby discharging the capacitor via a second resistor; measuring a second amount of time that corresponds to an amount of time between when the capacitor has the first voltage value and when the capacitor discharges to the second voltage value via the second resistor;
simultaneously closing the first switch and the second switch; measuring a third amount of time that corresponds to an amount of time between when the capacitor has the first voltage value and when the capacitor discharges to the second voltage value via the first resistor and the second resistor; and determining the sum of the COG resistance value and the FOG resistance value based at least in part on the first amount of time, the second amount of time, the third amount of time, and the matching error.