| 发明名称 | Three-dimensional two-port bit cell | ||
| 摘要 | A semiconductor memory includes a read port array disposed on a first layer of a three-dimensional integrated circuit and a bit cell array disposed on a second layer of the three-dimensional integrated circuit. The second layer being vertically positioned above or below the first layer. At least one bit cell of the bit cell array is coupled to at least one read port cell of the read port array by a via extending from the first layer to the second layer. | ||
| 申请公布号 | US9202557(B2) | 申请公布日期 | 2015.12.01 |
| 申请号 | US201314033537 | 申请日期 | 2013.09.23 |
| 申请人 | Taiwan Semiconductor Manufacturing Co., Ltd. | 发明人 | Wang Li-Wen;Chen Yen-Huei |
| 分类号 | G11C11/00;G11C11/419;H01L27/11;G11C8/16;H01L27/06;G11C5/02;G11C8/08;G11C11/412 | 主分类号 | G11C11/00 |
| 代理机构 | Duane Morris LLP | 代理人 | Duane Morris LLP |
| 主权项 | 1. A semiconductor memory, comprising: a read port array disposed on a first layer of a three-dimensional integrated circuit; and a bit cell array disposed on a second layer of the three-dimensional integrated circuit, wherein the second layer being vertically positioned above or below the first layer, and wherein each bit cell of the bit cell array is coupled to a respective read port cell of the read port array by a respective via extending from the first layer to the second layer. | ||
| 地址 | Hsin-Chu TW | ||