发明名称 Integrated circuit and method for monitoring bus status in integrated circuit
摘要 Embodiments of the present invention disclose an integrated circuit and a method for monitoring a bus status in the integrated circuit. Multiple status detectors and a top layer monitor are disposed in the integrated circuit. Each status detector in the multiple status detectors is used to read status data on a branch bus that is coupled to each status detector in the multiple status detectors, and then the top layer monitor collects the status data from each status detector, and outputs the status data through an interface.
申请公布号 US9201753(B2) 申请公布日期 2015.12.01
申请号 US201313754454 申请日期 2013.01.30
申请人 Huawei Technologies Co., Ltd. 发明人 Wang Haijun;Sun Xingguo;Tang Wei
分类号 G06F11/00;G06F11/34;G06F11/30 主分类号 G06F11/00
代理机构 代理人
主权项 1. An integrated circuit, comprising: a processor, a host bus, multiple branch buses, multiple status detectors, a top layer monitor, and an interface; wherein the multiple branch buses are coupled to the processor through the host bus; the host bus is configured to transmit data from the multiple branch buses to the processor; the processor is configured to perform data processing; each status detector in the multiple status detectors is coupled to a respective, corresponding branch bus in the multiple branch buses, and is configured to read status data on the corresponding branch bus that is coupled to the status detector, and upload the status data to the top layer monitor; and the top layer monitor is configured to collect the status data from each status detector, and output the status data through the interface, wherein the status data collected by each status detector reflects a status condition of the corresponding branch bus, the status condition corresponding to a volume of data that the corresponding branch bus bears.
地址 Shenzhen CN