发明名称 | Implementation method for fast NCL data path | ||
摘要 | An implementation method for a fast Null Convention Logic (NCL) data path includes a pipeline that is assembled from gates of various types of NCL. Self-ready flash NCL gates include a one-shot circuit to reset the gates to a null state and prepare the gates for the next wave of asserted data. In one embodiment, the one-shot circuit creates a flash pulse inside a gate in response to a change of a flash input line and ends the flash pulse in response to the gate output being reset to a null state. Conventional logic can be included in the data path as well. | ||
申请公布号 | US9203406(B2) | 申请公布日期 | 2015.12.01 |
申请号 | US201313894072 | 申请日期 | 2013.05.14 |
申请人 | Wave Semiconductor, Inc. | 发明人 | Singh Gajendra Prasad |
分类号 | H03K19/094;H03K19/00;G06F9/38 | 主分类号 | H03K19/094 |
代理机构 | Adams Intellex, PLC | 代理人 | Adams Intellex, PLC |
主权项 | 1. A logical pipeline comprising: a plurality of gates wherein the gates are comprised of: a plurality of transistors wherein the plurality of transistors provide for logical evaluation;a plurality of input lines, each having an asserted state and a null state, connected to one or more of the gates;a flash input line, having a first state and a second state, connected to one or more of the gates;an output line, having an asserted output state and a null output state, connected to one or more of the gates; and a data path formed from the plurality of gates wherein at least one gate includes a one-shot circuit wherein the one-shot circuit has an input attached to the flash input line and the one-shot circuit is used by the at least one gate to set the output line of the gate into the null output state. | ||
地址 | Campbell CA US |