| 发明名称 |
Diplexer design using through glass via technology |
| 摘要 |
A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate. |
| 申请公布号 |
US9203373(B2) |
申请公布日期 |
2015.12.01 |
| 申请号 |
US201313798733 |
申请日期 |
2013.03.13 |
| 申请人 |
QUALCOMM Incorporated |
发明人 |
Zuo Chengjie;Kim Jonghae;Velez Mario Francisco;Lan Je-Hsiung;Kim Daeik D.;Yun Changhan;Berdy David F.;Mikulka Robert P.;Nowak Matthew M.;Zhang Xiangdong;See Puay H. |
| 分类号 |
H03H7/46;H03H3/00;H05K1/16;H01L23/64;H03H1/00;H01L23/15;H01L23/498;H03H7/01;H01F17/00;H01L23/48;H01L23/522;H05K1/02;H05K1/03;H01L23/66 |
主分类号 |
H03H7/46 |
| 代理机构 |
|
代理人 |
Qiu Xiaotun |
| 主权项 |
1. A diplexer, comprising:
a substrate having a plurality of through substrate vias; a first plurality of traces on a first outer surface of the substrate, coupled to the plurality of through substrate vias; a second plurality of traces on a second outer surface of the substrate, opposite the first outer surface, coupled to opposite ends of the plurality of through substrate vias, the plurality of through substrate vias and traces operating as a 3D inductor; and a layered metal-insulator-metal capacitor structure directly supported by the first outer surface of the substrate and directly coupled to the 3D inductor. |
| 地址 |
San Diego CA US |
