Semiconductor device and method of making the same

摘要

A dual channel transistor includes a semiconductor island isolated by a first shallow trench isolation (STI) extending along a first direction and a second STI extending along a second direction, wherein the first direction intersect the second direction. The dual channel transistor further includes a gate trench recessed into the semiconductor island and extending along the second direction. A gate is located in the gate trench. A first U-shaped channel region is formed in the semiconductor island. A second U-shaped channel region is formed in the semiconductor island, wherein the second U-shaped channel region is segregate from the first U-shaped channel region by the gate. During operation, the gate controls two U-shaped channel regions simultaneously.

主权项

1. A semiconductor device having a dual channel transistor, comprising:
a semiconductor island isolated by at least a first shallow trench isolation extending along a first direction and a second shallow trench isolation extending along a second direction, wherein the first shallow trench isolation intersects the second shallow trench isolation; a gate trench extending along the second direction and recessed into the semiconductor island; a gate extending along the second direction and disposed at the gate trench; a first dielectric layer encapsulating the gate in the gate trench; a first source/drain regions disposed along the second direction and disposed with respect to a top surface of the semiconductor island; a second dielectric layer whose bottom is higher than that of the gate trench, embedded in the semiconductor island and disposed between the first source/drain regions; a first U-shaped channel region disposed around the second dielectric layer and between the first source/drain regions; a second source/drain regions disposed along the second direction and disposed with respect to the top surface of the semiconductor island; a third dielectric layer embedded in the semiconductor island and between the second source/drain regions; and a second U-shaped channel region disposed around the third dielectric layer and between the second source/drain regions.