发明名称 |
Trench high electron mobility transistor device |
摘要 |
A method for producing a solid state device, including forming a first dielectric layer over an epitaxial layer at least partially covering the a Silicon substrate and depositing a photoresist material thereover, removing a predetermined portion first dielectric layer to define an exposed portion, implanting dopants into the exposed portion to define a doped portion, preferentially removing Silicon from the exposed portion to generate trenches having V-shaped cross-sections and having first and second angled sidewalls defining the V-shaped cross-section, wherein each angled sidewall defining the V-shaped cross-section is a Silicon face having a 111 orientation, and forming a 2DEG on at least one sidewall. |
申请公布号 |
US9202888(B2) |
申请公布日期 |
2015.12.01 |
申请号 |
US201414307215 |
申请日期 |
2014.06.17 |
申请人 |
|
发明人 |
Barlow Stephen P. |
分类号 |
H01L29/778;H01L29/66;H01L29/20;H01L29/205;H01L29/04;H01L29/06;H01L29/49;H01L29/417;H01L29/45;H01L29/10;H01L21/306;H01L21/8258 |
主分类号 |
H01L29/778 |
代理机构 |
Brannon Sowers and Cracraft PC |
代理人 |
Brannon C. John;Brannon Sowers and Cracraft PC |
主权项 |
1. A transistor device, comprising:
a crystalline silicon substrate member; a first substantially flat surface formed on the substrate member; a second oppositely disposed surface formed on the substrate member and spaced from the first surface; a third surface formed on the substrate member and extending from the first surface and following a 111 orientation plane; a source structure formed in the first surface; a gate structure formed in the first surface and spaced from the source structure; a drain structure formed on the second surface; a dielectric layer formed on the first surface; a p-well formed in the first surface and positioned between the gate structure and the source structure; wherein the dielectric layer is between about 10 microns thick and about 200 microns thick; and wherein the third surface hosts a 2-dimensional electron gas. |
地址 |
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